A conventional ferroelectric capacitor includes one or more ferroelectric layers sandwiched between a bottom electrode and a top electrode. The ferroelectric layer(s) may include, for example, PZT, SBT or BLT. The capacitor is covered with one or more interlayer dielectric layers, normally Tetraethyl Orthosilicate (TEOS), and connection to the top electrode is achieved by etching a window through the interlayer dielectric layer(s) and filling the window with a metal filler. The bottom electrode is mounted on a substrate, the electrical connection to the bottom electrode being via a metal plug through the substrate. To make the connection between the bottom electrode and the plug, a window is formed through the interlayer dielectric layer(s), through the other layers of the capacitor and into the plug. A liner is formed in this window and a metal filler is deposited in the bottom of the window to make the contact between the bottom electrode and the plug. The liner and the metal filler are etched to leave just the contact to the plug. Encapsulation layers and cover layers are added to protect the resultant capacitor.
In the production of conventional capacitors it is known to etch the top and bottom electrodes in separate processes, and, in each case, a hardmask is used to define the etch pattern. Normally, after etching, the remainder of the hardmask is left in situ and further layers are deposited over the remnants of the hardmask, as required, and these remnants and layers are incorporated into the final device. This increases the height of the resultant capacitor device.
A number of problems may arise due to the typical height of conventional ferroelectric capacitors (around 17600 Angstroms (A), about one third of which is due to the presence of the hardmask layers). For example, the typical aspect ratio between the length of the window to the bottom electrode and the width of the window (typically 4:1) makes it difficult to deposit a liner (of, for example, VO) therein. Furthermore, due to the height of conventional capacitors, it is difficult to include a number of such capacitors in a device where space is limited.
In view of the foregoing problems with conventional processes and devices, a need exists for an easily applied method for producing capacitors of less than conventional height without reducing production yield or compromising performance.